In recently-developed merged memory logic (MML), a memory cell array such as dynamic random access memory (DRAM) and a logic array such as analog circuits or peripheral circuits are integrated in a single chip. With the advent of MML, multimedia functions have been greatly improved and, therefore, the high-integration and the high-speed operation of semiconductor device have been achieved more effectively.
To achieve the high-speed operation of analog circuits, a capacitor with high capacitance is in development. Generally, in a capacitor of polysilicon-insulator-polysilicon (PIP) structure, the interface between dielectric and upper/lower electrodes may be oxidized to form a natural oxide layer because the upper and lower electrodes are made of polysilicon. Such a natural oxide layer may lower the total capacitance of the capacitor. In addition, the capacitance of the capacitor may be reduced due to depletion regions that are created in the polysilicon layer. Such capacitors with low capacitance are unsuitable for use in devices requiring high-speed and high-frequency operation.
To obviate these problems, new capacitor structures such as metal-insulator-silicon (MIS) and metal-insulator-metal (MIM) have been suggested. Particularly, the MIM capacitor is broadly used in high performance semiconductor devices because it has low specific resistance and no parasitic capacitance due to depletion regions. Recently, technology for forming a metal interconnect of a semiconductor device using copper with low specific resistance instead of aluminum has been introduced. Therefore, various MIM capacitors with copper electrodes are being suggested.
FIGS. 1a and 1b are cross-sectional views illustrating a conventional process of fabricating an MIM capacitor and a dual damascene structure interconnect of a semiconductor device. As shown in FIG. 1a, a lower insulating layer 10 is deposited on a semiconductor substrate 1. A first metal interconnect 15 and a second metal interconnect 20 are then formed in the lower insulating layer 10. After a metal layer is deposited over the resulting structure, some portion of the metal layer is removed to form a lower electrode 25 of a capacitor on the second metal interconnect 20. A dielectric layer 30 is then deposited over the semiconductor substrate 1 including the lower capacitor electrode 25. After another metal layer is deposited on the dielectric layer 30, some portion of the another metal layer is removed to form an upper electrode 35 of a capacitor on the lower electrode 25. Next, an interlayer dielectric (ILD) layer 40 is deposited over the resulting structure.
Referring to FIG. 1b, the ILD layer 40 is planarizied by using a chemical mechanical polish (CMP) process. Some portion of the ILD layer 40 and dielectric layer 30 is then removed by using an etching process to form a via hole V1 through the ILD layer 40. The via hole V1 exposes some portion of the top surface of the first metal interconnect 15. Next, a first trench T1 is formed in the upper part of the via hole V1. A second trench T2 is formed through the ILD layer 40 on the upper electrode 35. The second trench T2 exposes some portion of the top surface of the upper electrode 35. The via hole V1, the first trench T1, and the second trench T2 are filled with copper and then planarized by using a CMP process. As a result, a damascene structure interconnect 45 and a contact plug 50 are completed.
However, the above-mentioned conventional process of fabricating an MIM capacitor and a dual damascene structure interconnect has several problems. First of all, the conventional process requires an additional metal interconnect process to form a metal interconnect to apply a bias to the lower electrode of the capacitor. In addition, the conventional process is rather complicated because the via hole and the trench on the upper electrode are formed by using separate unit processes.
In other respects, as utilization of a capacitor in logic devices increases, a capacitor with high capacitance is desperately required. Generally, the capacitance (C) of a capacitor is represented by the equation as follows:C=∈As/dWhere ∈ is the dielectric constant, As is the surface area of an electrode, and d is the thickness of dielectric.
Referring to the above-mentioned equation, there are three methods to increase the capacitance (C) of a capacitor within a limited unit surface area. The three methods are decreasing the thickness of dielectric (d) of a capacitor, increasing the surface area of the electrode (As) of a capacitor, and using materials with high dielectric constant (∈). Among them, to mention increasing the surface area of the electrode of a capacitor, a conventional analog capacitor has a limited two-dimensional active surface area because they use metal interconnects that connect various kinds of devices as the upper and lower electrodes of the capacitor.
FIGS. 2a through 2e are cross-sectional views illustrating a conventional process of fabricating an MIM capacitor and a contact plug of a semiconductor device. As shown in FIG. 2a, an ILD layer 2 is deposited on a substrate (not shown) having at least one predetermined structure. A metal layer is deposited on the ILD layer 2. Some portion of the metal layer is then removed to make a lower electrode 4a of a capacitor and a lower interconnect 4b. An inter-metal dielectric (IMD) layer 6 is deposited over the substrate including the ILD layer 2, the lower electrode 4a, and the lower interconnect 4b, and planarized by using a planarization process.
Referring to FIG. 2b, a contact hole 8 is formed through the IMD layer 6 on the lower electrode 4a by using a photolithography process. The contact hole 8 exposes some portion of the top surface of lower electrode 4a. The exposed top surface of lower electrode 4a becomes an active surface area of a capacitor.
Referring to FIG. 2c, a dielectric layer 10 is deposited on the structure of FIG. 2b. 
Referring to FIG. 2d, a via hole 12 is formed through the dielectric layer 10 on the lower interconnect 4b by using a photolithography process. The via hole 12 exposes some portion of the top surface of lower interconnect 4b. 
Referring to FIG. 2e, a conductive layer is deposited on the structure of FIG. 2d. Some portion of the conductive layer is removed to form an upper electrode 14a of a capacitor and an upper interconnect 14b. 
However, the above-mentioned conventional MIM capacitor is subject to limitations in increasing the capacitance because it has a two-dimensional active surface area.